UPD45128163 查看數據表（PDF） - NEC => Renesas Technology

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UPD45128163

128M-bit Synchronous DRAM 4-bank, LVTTL

NEC => Renesas Technology 

Block Diagram

CLK

CKE

Clock

Generator

Address

Mode

Register

/CS

/RAS

/CAS

/WE

µPD45128441, 45128841, 45128163

Row

Address

Buffer

&

Refresh

Counter

Column

Address

Buffer

&

Burst

Counter

Bank D

Bank C

Bank B

Bank A

Sense Amplifier

Column Decoder &

Latch Circuit

Data Control Circuit

DQM

DQ

Data Sheet M12650EJBV0DS00

7

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