A63L73321 查看數據表（PDF） - AMIC Technology

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A63L73321

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output

AMIC Technology 

Timing Waveforms

CLK

ADSP

ADSC

ADDRESS

GW,BWE

BW1-BW4

CE

(NOTE 2)

ADV

tKC

tKH

tKL

tADSS

tADSH

tADSS

tADSH

tAS

tAH

A1

tWS

A2

tWH

tCES

tCEH

tADVS

tADVH

OE

DOUT

(NOTE 3)

High-Z

tOEQ

tKQLZ

tKQ

tOELZ

tOEHZ

Q(A1)

Single READ

tKQ

tKQX

Q(A2)

Q(A2+1)

(NOTE *1)

A63L73321 Series

Deselect cycle

(Note 4)

ADV suspends burst

Q(A2+2)

Q(A2+3)

BURST READ

Q(A2)

Q(A2+1)

Burst wraps around

to its initial state

tKQHZ

Q(A2+2)

Read Timing

Don't Care

Undefined

Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following

A2.

2. CE and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH.

When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not

cause Q to be driven until after the following clock rising edge.

4. Outputs are disabled tKQHZ after deselect.

PRELIMINARY (June, 1999, Version 0.1)

11

AMIC Technology, Inc.

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