A61L6316S-10 查看數據表（PDF） - AMIC Technology

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A61L6316S-10

64K X 16 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

Timing Waveforms

Read Cycle 1(1, 2, 4)

Address

DOUT

tRC

tAA

tOH

A61L6316 Series

tOH

Read Cycle 2(1, 2, 3)

Address

CE

HB, LB

OE

DOUT

tRC

tAA

tCLZ 5

tACE

tBE

tBLZ5

tOE

tOLZ 5

tCHZ 5

tBHZ5

tOHZ5

Notes:

1. WE is high for Read Cycle.

2. Device is continuously enabled CE = VIL, HB = VIH and, or LB = VIL.

3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

(May, 2001, Version 1.0)

7

AMIC Technology, Inc.

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