MX98726EC 查看數據表（PDF） - Macronix International

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MX98726EC

SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Macronix International 

MX98726EC

GMAC Test Register A : TRA (Reg02h),R/W, default=00h

Bit

2.0

2.1-2.3

2.4

2.5

2.6

2.7

Symbol

TEST

TMODE[2:0]

RWR

RWD

FC

SB

Description

Test mode enable: Set to enable test modes defined by TMODE[2:0], default is reset

for normal operation.

Test Mode Select bits[2:0]: Reserved for GMAC's internal tests, only meaningful when

the TEST bit is set, except when TMODE [2:0] = "110" which is also used as normal

mode with EEPROM interface disabled. When TMODE [2:0] = "110" & Test =0, then

MA19~MA16 are still SRAM address bit19~16, while Test = 1, MA19~MA16 are de-

fined as test pins reserved for debug purpose.

Receive Watchdog Release : When set, the receive watchdog is released 40 to 48 bit

times from the last carrier deassertion. When reset, the receive watchdog is released

16 to 24 bits times from the last carrier deassertion.

Receive Watchdog Disable : When set, the receive watchdog is disabled. When reset,

receive carriers longer than 2560 bytes are guaranteed to cause the watchdog timeout.

Packets shorted than 2048 bytes are guaranteed to pass.

Forced Collision : Set to force collision at every transmit packet, this bit works only in

internal FIFO loopback mode, i.e. LB0=1, LB1=0, to test excessive collision. Default

is reset.

Start/Stop Backoff counter: When set, indicates internal backoff counter stops count-

ing when any carrier is detected. Counter resumed when carrier drops. When reset,

the internal backoff counter is not affected by carrier activity. Default is reset.

GMACTest Register :TRB (Reg03h),R/W, default=00h

Bit

Symbol

Description

3.0

FKD*

Flaky Oscillator Disable: When set, indicates that the internal flaky

oscillator is disabled. Pseudo random numbers are chosen instead of

fully random numbers, used for the internal diagnostic purpose. Set to

disable the normal clocking scheme in the timer's test. Reset to enable

the timer test. Default is reset.

3.1

RDNCNTCB*

Reserved for test

3.2

RDNCNTSB*

Reserved for test

3.3

COLCNTCB*

Reserved for test

3.4

BFS0*(MDC)

Normally used as BFS0 pin for test purpose, while in MII mode, it is

defined as MII management clock signal (MDC) to be used as a timing

reference of MDIO pin.

3.5

BKCNTLB*(MDIOEN)

Normally used as BKCNTLB pin for test purpose, while in MII mode, it is

used to control the direction of MDIO pin. Set MDIOEN = 1 will make

MDIO pin as input pin, the value can be read from MDI bit.

Set MDIOEN = 0 will make MDIO pin as output pin, the value of MDO bit

is driven out to MDIO pin.

3.6

BFS1*(MDO)

Normally used as BFS1 pin for test purpose, while in MII mode, it is

used as MII management write data (MDO) for MDIO pin's output data.

3.7

BFSTATUS*(MDI)

Normally used as BFSTATUS pin for test purpose, while in MII mode, it is

used as MII management read data (MDI) for MDIO pin's input data.

P/N:PM0729

REV. 1.1, MAY. 28, 2001

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