M37640E8 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
2.3.2 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock
fSYN that are both a multiple of the external input reference clock fIN. A block diagram of the circuit
is shown in Figure 2-8.
fIN
Prescaler fPIN
Frequency
Multiplier
fSYN
fVCO
Frequency
Divider
fUSB
FSM2
006E
FSM1
006D
LS
FSC
006C
8 Bit
FSD
006F
Data Bus
Figure 2-8. Frequency Synthesizer Circuit
The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider
macro, and four registers, namely FSM1, FSM2, FSC and FSD. Two multiply registers (FSM1, FSM2)
control the frequency multiply amount. Clock fIN is prescaled using FSM2 to generate fPIN. fPIN is
multiplied using FSM1 to generate an fVCO clock which is then divided using FSD to produce the
clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the
frequency synthesizer block as signal fUSB. This signal is used by the USB block.
Clock fPIN is a divided down version of clock fIN, which can be either fXin or fXCin. The default clock
after reset is fXin. The relationship between fPIN and the clock input to the prescaler (fIN) is as
follows:
• fPIN = fIN / 2(n+1) where n is a decimal number between 0 and 254. Setting FSM2 to 255
disables the prescaler and fPIN = fIN.
MSB
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
fPIN
24 MHz
1 MHz
2 MHz
3 MHz
6 MHz
12 MHz
FSM2
Dec(n)
Hex(n)
255
FF
11
0C
5
05
3
03
1
01
0
00
fIN/2(n+1) = fPIN
Bit 2
Bit 1
fIN
24.00 MHz
24.00 MHz
24.00 MHz
24.00 MHz
24.00 MHz
24.00 MHz
Bit 0
LSB Address: 006E16
0
Access: R/W
Reset: FF16
Figure 2-9. Frequency Synthesizer Multiply Control Register FSM2
Oscillator Circuit
7/9/98
2-11
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