XRT71D00IQ 查看數據表（PDF） - Exar Corporation
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XRT71D00IQ Datasheet PDF : 26 Pages
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
MICROPROCESSOR SERIAL INTERFACE TIMING ( SEE FIGURE 4 )
SYMBOL
PARAMETER
t21 CS Low to Rising Edge of SClk Setup Time
t22 SClk to CS Hold Time
t23 SDI to Rising Edge of SClk Setup Time
t24 SDI to Rising Edge of SClk Hold Time
t25 SClk “Low” Time
t26 SClk “High” Time
t27 SClk Period
t28 SClk to CS Hold Time
t29 CS “Inactive” Time
t30 Falling Edge of SClk to SDO Valid Time
t31 Falling Edge of SClk to SDO Invalid Time
t32 Falling Edge of SClk, or rising edge of CS to High Z
MIN
TYP
MAX
UNITS.
50
ns
20
ns
50
ns
50
ns
240
ns
240
ns
500
ns
50
ns
250
ns
200
ns
100
ns
100
ns
FIGURE 4. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
CS
SClk
SDI
t21
t22
t23
t24
R/W
t27
t25
t26
A0
A1
t29
t28
CS
SClk
t30
t31
SDO Hi-Z
D0
D1
Hi-Z
SDI
t33
D2
t32
D7
10
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