MT9160AE 查看數據表（PDF） - Mitel Networks
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MT9160AE Datasheet PDF : 28 Pages
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Preliminary Information
MT9160
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT9160 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
µ-Law functionality, usually 0 dB programmable
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
5V Multi-featured Codec Register Map
00
RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 Gain Control
Register 1
01
-
-
-
-
-
STG2
STG1
STG0 Gain Control
Register 2
02
-
-
-
-
-
-
-
DrGain Path Control
03
PDFDI PDDR
RST
-
TxMute RxMute TxBsel RxBsel
Control
Register 1
04
CEN
DEN
D8
A/µ
Smag/
CSL2
CSL1
CSL0
Control
CCITT
Register 2
05
C7
C6
C5
C4
C3
C2
C1
C0
C-Channel
Register
06
D7
D6
D5
D4
D3
D2
D1
D0
D-Channel
Register
07
-
-
-
-
PCM/ loopen
-
-
Loop Back
ANALOG
7-87
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