W196 查看數據表（PDF） - Cypress Semiconductor

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W196

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

Cypress Semiconductor 

PRELIMINARY

W196

48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

f

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

fD

Deviation from 48 MHz

(48.008 – 48)/48

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

tR

Output Rise Edge Rate Measured from 0.4V to 2.4V

tF

Output Fall Edge Rate

Measured from 2.4V to 0.4V

tD

Duty Cycle

Measured on rising and falling edge at 1.5V

fST

Frequency Stabilization Assumes full supply voltage reached within 1 ms

from Power-up (cold start) from power-up. Short cycles exist prior to fre-

quency stabilization.

Zo

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

Min. Typ. Max.

48.008

24.004

+167

57/17, 57/34

0.5

2

0.5

2

45

55

3

25

Unit

MHz

ppm

V/ns

V/ns

%

ms

Ω

Ordering Information

Ordering Code

W196

Package

Name

G

Package Type

28-pin SOIC (300 mils)

Document #: 38-07170 Rev. *A

Page 10 of 12

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