STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

1 GENERAL DESCRIPTION

At the heart of the STPC Atlas is an advanced

processor block that includes a powerful x86

processor core along with a 64-bit SDRAM

controller, advanced 64-bit accelerated graphics

and video controller, a high speed PCI bus

controller and industry standard PC chip set

functions (Interrupt controller, DMA Controller,

Interval timer and ISA bus).

The STPC Atlas has in addition, a TFT output, a

Video Input, an EIDE controller, a Local Bus

interface, PCMCIA and super I/O features

including USB host hub.

1.1. ARCHITECTURE

1.2. GRAPHICS FEATURES

Graphics functions are controlled through the on-

chip SVGA controller and the monitor display is

produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing operations which include

hardware acceleration of text, bitblts, transparent

blts and fills. The results of these operations

change the contents of the on-screen or off-screen

frame buffer areas of SDRAM memory. The frame

buffer can occupy a space up to 4 Mbytes

anywhere in the physical main memory.

The STPC Atlas makes use of a tightly coupled

) Unified Memory Architecture (UMA), where the

t(s same memory array is used for CPU main memory

and graphics frame-buffer. This means a reduction

c in total system memory for system performances

u that are equal to that of a comparable frame buffer

d and system memory based system, and generally

ro much better, due to the higher memory bandwidth

allowed by attaching the graphics engine directly

P to the 64-bit processor host interface running at

te the speed of the processor bus rather than the

traditional PCI bus.

ole The 64-bit wide memory array provides the system

s with an 800MB/s peak bandwidth. This allows for

b higher resolution screens and greater color depth.

O The processor bus runs at 133 MHz, further

- increasing “standard” bandwidth by at least a

) factor of two.

t(s The ‘standard’ PC chipset functions (DMA,

c interrupt controller, timers, power management

u logic) are integrated together with the x86

d processor core; additional low bandwidth functions

ro such as communication ports are accessed by the

STPC Atlas via an internal ISA bus.

te P The PCI bus is the main data communication link

to the STPC Atlas chip. The STPC Atlas translates

le appropriate host bus I/O and Memory cycles onto

o the PCI bus. It also supports the generation of

s Configuration cycles on the PCI bus. The STPC

bAtlas, as a PCI bus agent (host bridge class), is

Ocompatible with PCI specification 2.1. The chip-set

The maximum graphics resolution supported is

1280 x 1024 in 16 Million colours at 75 Hz refresh

rate and is VGA and SVGA compatible. Horizontal

timing fields are VGA compatible while the vertical

fields are extended by one bit to accommodate

above display resolution.

To generate the TFT output, the STPC Atlas

extracts the digital video stream before the

RAMDAC and reformats it to the TFT format. The

height and width of the flat panel are

programmable.

1.3. INTERFACES

An industry standard EIDE (ATA 2) controller is

built in to the STPC Atlas and connected internally

via the PCI bus.

The STPC Atlas integrates two USB ports.

Universal Serial Bus (USB) is a general purpose

communications interface for connecting

peripherals to a PC. The USB Open Host

Controller Interface (Open HCI) Specification,

revision 1.1, supports speeds of up to 12 MB/s.

USB is royalty free and is likely to replace low-

speed legacy serial, parallel, keyboard, mouse

and floppy drive interfaces. USB Revision 1.1 is

fully supported under Microsoft Windows 98 and

Windows 2000.

The STPC Atlas PCMCIA controller has been

specifically designed to provide the interface with

also implements the PCI mandatory header PCMCIA cards which contain additional memory

registers in Type 0 PCI configuration space for or I/O

easy porting of PCI aware system BIOS. The

device contains a PCI arbitration function for three

external PCI devices.

The power management control facilities include

socket power control, insertion/removal capability,

power saving with Windows inactivity, NCS

Figure 1-1 describes this architecture.

controlled Chip Power Down, together with further

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