FX805 查看數據表（PDF） - CML Microsystems Plc

零件编号

产品描述 (功能)

比赛名单

FX805

Sub-audio signalling processor

CML Microsystems Plc 

Pin Number Function

FX805

J/LG/LS

1

Xtal: The output of the on-chip clock oscillator. External components are required at this input when a

Xtal (f ) input is used. See Figure 2.

XTAL

2

Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (f )

XTAL

should be connected here. See Figure 2.

3

Address Select: This pin enables two FX805 devices to be used on the same “C-BUS,” providing full-

duplex operation. See Tables 1 and 2.

4

Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by

going to a logic “0.” This is a “wire-or able” output, allowing the connection of up to 8 peripherals to 1

interrupt port on the µController. This pin has a low impedance pulldown to logic “0” when active and a

high impedance when inactive. The System IRQ line requires 1 pullup resistor to VDD. The conditions

that cause interrupts are indicated in the Status Register (Table 4) and are shown below:

Rx CTCSS Tone Measurement Complete

1 NRZ Rx Data Byte Received

NRZ Tx Buffer Ready

CTCSS NOTONE Timer Expired

New NRZ Rx Data Received Before Last Byte Read

NRZ Data Transmission Complete

5

Serial Clock: The “C-BUS” serial clock input. This clock, produced by the µController, is used for

transfer timing of commands and data to and from the Sub-Audio Signalling Processor. See Timing

Diagrams.

6

Command Data: The “C-BUS” serial data input from the µController. Data is loaded to this device in

8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams.

7

Chip Select (CS): The “C-BUS” data loading control function. This input is provided by the

µController. Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing

Diagrams.

8

Reply Data: The “C-BUS” serial data output to the µController. The transmission of Reply Data bytes

is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held

at high impedance when not sending data to the µController. See Timing Diagrams.

9

Tx Sub-Audio Out: The sub-audio output (pure or NRZ derived). Signals are band-limited, the Tx

Output Filter has a variable bandwidth, see Table 6. This output is at V (a) when the NRZ Encoder

BIAS

is enabled but no data is being transmitted, (b) when the FX805 is placed in the Powersave All

condition.

10

Audio In: The input to the switched sub-audio bandstop (highpass) filter. This input is internally biased

and requires to be a.c. coupled by capacitor C7.

11

Audio Out: The output of the ‘audio signal path’ (filter or by-pass). This output is controlled by the

Control Register and when disabled is held at VDD/2.

12

V : Negative Supply (Signal Ground).

SS

2

Share Link: