GS832236C-133 查看數據表（PDF） - Giga Semiconductor

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比赛名单

GS832236C-133

2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Giga Semiconductor 

Preliminary

GS832218(B/E)/GS832236(B/E)/GS832272(C)

GS832272 209-Bump BGA Pin Description

Symbol

A0, A1

An

DQA

DQB

DQC

DQD

DQE

DQF

DQG

DQH

BA, BB

BC,BD

BE, BF, BG,BH

NC

CK

GW

E1

E3

E2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

SCD

MCH

MCL

BW

ZQ

TMS

TDI

TDO

TCK

Type

I

I

I/O

I

I

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

Description

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

Data Input and Output pins

Byte Write Enable for DQA, DQB I/Os; active low

Byte Write Enable for DQC, DQD I/Os; active low

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

No Connect

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Must Connect High

Must Connect Low

Byte Enable; active low

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Rev: 1.06 9/2004

3/41

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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