GS881Z32BD-133I 查看數據表（PDF） - Giga Semiconductor

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GS881Z32BD-133I

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)

GS881Z18/32/36BD 165-Bump BGA Pin Description

Symbol

A0, A1

An

A17, A18, A19

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

BA, BB, BC, BD

NC

CK

CKE

W

E1

E3

E2

G

ADV

ZZ

FT

LBO

TMS

TDI

TDO

TCK

MCH

DNU

VDD

VSS

VDDQ

Type

I

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

—

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

Clock Input Signal; active high

Clock Enable; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active high

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect High

Do Not Use

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.00b 12/2002

8/37

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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