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MM1145BF 查看數據表(PDF) - Mitsumi

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MM1145BF Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
MITSUMI
System Reset (with built-in watchdog timer) MM1145
Electrical Characteristics (DC) (Except where noted otherwise, Ta=25°C, VCC=5.0V)
(Except where noted otherwise, resistance unit is )
Item
Symbol Measurement conditions
Min. Typ. Max. Units
VCC input pulse width
5.0V
TPI VCC
4.0V
8
µs
TCKW1
CK input pulse width
CK
or
3
µs
TCKW2
TCK1
* CK input cycle 7
TCK2
or
200
µs
Watchdog timer MM1145A
TWD
* monitoring time 1 MM1145B
Watchdog timer MM1145A
TWR
* reset time 2 MM1145B
Reset hold time for MM1145A
TPR
* power supply rise 3 MM1145B
* Output delay time from VCC 4 TPD
* Output rise time 5
tR
* Output fall time 5
tF
CT=0.02µF, RRCT=1M
CT=0.02µF, RRCT=1M
CT=0.02µF
RRCT=1M
VCC
--------------------------------------------------------------------------------------
RESET pin, RL=10k, CL=20pF
--------------------------------------------------------------------------------------
RESET pin, RL=10k, CL=20pF
--------------------------------------------------------------------------------------
RESET pin, RL=10k, CL=20pF
40 50 60
ms
80 110 140
5
10 15
ms
5
10 15
50 100 150
ms
20 40 60
2
10
µs
2.0 4.0
µs
0.2 1.0
µs
Notes:
*1 Monitoring time is the time from the last pulse (negative edge) of the timer clear clock pulse until reset
pulse output.
In other words, reset output is output if a clock pulse is not input during this time.
*2 Reset time means reset pulse width. However, this does not apply to power ON reset.
*3 Reset hold time is the time from when VCC exceeds detection voltage (VSHR) during power ON reset until
------------------------------------------------
reset release (RESET output high).
*4 Output delay time is the time from when power supply voltage drops below detection voltage (VSL) until
------------------------------------------------
reset state occurs (RESET output low).
*5 The voltage range when measuring output rise and fall time is 10~90%.
*7 1 Set CK1 and CK2 input cycles within the following range.
TCK1 <= nTCK2<TWD (ms) (n <= 1)
------------------------------------------------
RESET output may go low even if CK1 and CK2 are input without these conditions being met.
(Recommended use is for TCK1 <= nTCK2)
2 TCK1, TCK2 <= 200 µs results in the following operation.
Discharge switches to charging with the CK2 pulse (negative edge) that inputs 200µs after CT switches
------------------------------------------------
from charging to discharge by the CK2 pulse (negative edge). RESET output stays high while this
operation is being repeated. (However, TCK1, TCK2 >= 20µs.)

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