ADG511BR 查看數據表（PDF） - Analog Devices
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ADG511BR Datasheet PDF : 12 Pages
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ADG511/ADG512/ADG513
0.006
0.004
VDD = +5V
VSS = –5V
TA = +25؇C
0.002
0.000
–0.002
ID (ON)
ID (OFF)
IS (OFF)
–0.004
–0.006
–5 –4 –3 –2 –1 0 1 2 3 4 5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
TPC 7. Leakage Currents as a Function of VD (VS)
110
VDD = +5V
VSS = –5V
100
90
80
70
60
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 8. Crosstalk vs. Frequency
APPLICATION
Figure 1 illustrates a precise sample-and-hold circuit. An AD845
is used as the input buffer while the output operational ampli-
fier is an OP07. During the track mode, SW1 is closed and the
output VOUT follows the input signal VIN. In the hold mode,
SW1 is opened and the signal is held by the hold capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG511/ADG512/
ADG513 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15 µV/µs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation
network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ± 3 V input range.
The acquisition time is 2.5 µs while the settling time is 1.85 µs.
+5V
VIN
AD845
–5V
+5V
SW2
S
SW1
S
2200pF
+5V
D
RC
75⍀
CC
1000pF
D
CH
2200pF
OP07
–5V
ADG511/
ADG512/
ADG513
VOUT
–5V
Figure 1. Accurate Sample-and-Hold
TRENCH ISOLATION
The MOS devices that make up the ADG511A/ADG512A/
ADG513A are isolated from each other by an oxide layer
(trench) (see Figure 2). When the NMOS and PMOS devices
are not electrically isolated from each other, there exists the
possibility of “latch-up” caused by parasitic junctions between
CMOS transistors. Latch-up is caused when P-N junctions that
are normally reverse biased, become forward biased, causing
large currents to flow. This can be destructive.
CMOS devices are normally isolated from each other by Junction
Isolation. In Junction Isolation the N and P wells of the CMOS
transistors form a diode that is reverse biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A Silicon-Controlled Rectifier (SCR)-
type circuit is formed by the two transistors, causing a signifi-
cant amplification of the current that, in turn, leads to latch-up.
With Trench Isolation, this diode is removed; the result is a
latch-up-proof circuit.
VS
VG
VD
VS
VG
VD
T
R
P+ P-CHANNEL P+
T
R
N+ N-CHANNEL N+
T
R
E
E
E
N
N
N
C
H
N–
C
H
P–
C
H
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
Figure 2. Trench Isolation
–8–
REV. C
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