CXD2463R 查看數據表（PDF） - Sony Semiconductor

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CXD2463R

Timing Controller for CCD Camera

Sony Semiconductor 

CXD2463R

Pin

No.

Symbol

I/O

Description

15 BLC

O Window pulse output for backlight compensation

16 VSS1

— GND

17 BLCW1

I Window select 1 for backlight compensation (with pull-down resistor)

18 BLCW2

I Window select 2 for backlight compensation (with pull-down resistor)

19 VDD1

— Power supply

20 ESHUT2

I Sub pulse control (with pull-down resistor)

21 ESHUT1

I Sub pulse control (with pull-down resistor)

22 TEST

I Fixed low (with pull-down resistor)

23 CLP1

O Clamp pulse output

24 CLP2

O Clamp pulse output

25 SYNC

O Composite sync output

26 CBLK

O Composite blanking output

27 EIA

I Low: EIA, High: CCIR (with pull-down resistor)

28 CCD

I Low: 510H, High: 760H (with pull-down resistor)

29 RST

I Reset (low reset). Always input reset pulse after power-on.

30 SHD

O Data sample-and-hold pulse

31 SHP

O Precharge level sample-and-hold pulse

32 VSS2

— GND

33 HVDET

O

Horizontal PLL/Vertical PLL discrimination signal

High: Vertical PLL, Low: Horizontal PLL

34 EXT

O

External sync/internal sync discrimination signal

High: External sync, Low: Internal sync

35 VD

O Vertical drive output

36 HD

O Horizontal drive output

37 EVD

I Vertical drive signal input (with pull-up resistor)

38 EHD/SYNC I Horizontal drive signal input/Composite sync input (with pull-up resistor)

39 COMP

O Comparator output

40 LCIN

I Inverter input for oscillation

41 LCOUT

O Inverter output for oscillation

42 CKI

I 2MCK input

43 VDD2

— Power supply

44 AVDD

— Power supply (for H1, H2, and RG)

45 H1

O H1 clock output for CCD horizontal register drive

46 H2

O H2 clock output for CCD horizontal register drive

47 AVSS

— GND (for H1, H2, and RG)

48 RG

O Reset gate pulse output

–4–

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