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ST16C1550CQ48(2005) 查看數據表(PDF) - Exar Corporation

零件编号
产品描述 (功能)
比赛名单
ST16C1550CQ48
(Rev.:2005)
Exar
Exar Corporation Exar
ST16C1550CQ48 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
xr
REV. 4.2.1
PIN DESCRIPTIONS
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
NAME
28-PIN 28-PIN
PLCC PLCC
(1550) (1551)
48-PIN
TQFP
TYPE
DESCRIPTION
DATA BUS INTERFACE
A0
21
21
30
I Address data lines [2:0]. A2:A0 selects internal UART’s configuration regis-
A1
20
20
28
ters.
A2
19
19
27
D0
1
1
43 I/O Data bus lines [7:0] (bidirectional).
D1
2
2
45
D2
3
3
46
D3
4
4
47
D4
5
5
3
D5
6
6
4
D6
7
7
5
D7
8
8
6
IOR# 16
15
20
I Input/Output Read (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the
address lines [A2:A0], places it on the data bus to allow the host processor to
read it on the leading edge.
IOW# 14
13
17
I Input/Output Write (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal
register pointed by the address lines [A2:A0].
CS# 11
11
9
I Chip Select input (active low). A logic 0 on this pin selects the ST16C155X
device.
INT
18
18
23
O Interrupt Output (three-state, active high). INT output defaults to three-state
mode and becomes active high when MCR bit-3 is set to a logic 1. INT output
becomes a logic high level when interrupts are enabled in the interrupt enable
register (IER), and whenever the transmitter, receiver, line and/or modem sta-
tus register has an active condition.
MODEM OR SERIAL I/O INTERFACE
TX
10
10
8
O Transmit Data. This output is associated with individual serial transmit chan-
nel data from the 155X. The TX signal will be a logic 1 during reset, idle (no
data), or when the transmitter is disabled. During the local loopback mode, the
TX output pin is disabled and TX data is internally connected to the UART RX
input.
RX
9
9
7
I Receive Data. This input is associated with individual serial channel data to
the 155X. Normal received data input idles at logic 1 condition. This input
must be connected to its idle logic state, logic 1, else the receiver may report
“receive break” and/or “error” condition(s).
RTS# 22
22
31
O Request to Send or general purpose output (active low). If this pin is not
needed for modem communication, then it can be used as a general I/O. If it
is not used, leave it unconnected.
CTS# 25
25
34
I Clear to Send or general purpose input (active low). If this pin is not needed
for modem communication, then it can be used as a general I/O. If it is not
used, connect it to VCC.
5

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