V53C8129H50 查看數據表（PDF） - Mosel Vitelic Corporation

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V53C8129H50

ULTRA-HIGH PERFORMANCE, 128K X 8 EDO PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic Corporation  

MOSEL VITELIC

V 5 3C 8 1 2 9 H

V53C8129H

FAMILY

Description Pkg. Pin Count

SOJ

K

26/24

DEVICE

PKG SPEED

TEMP.

. ( tRAC) PWR.

BLANK (0°C to 70°C)

K (SOJ)

BLANK (NORMAL)

35 (35 ns)

40 (40 ns)

45 (45 ns)

50 (50 ns)

8129H-01

26/24 Lead SOJ

PIN CONFIGURATION

Top View

VSS 1

I/O1 2

I/O2 3

I/O3 4

I/O4 5

WE 6

RAS 8

A0 9

A1 10

A2 11

A3 12

VCC 13

26 VSS

25 I/O8

24 I/O7

23 I/O6

22 I/O5

21 CAS

19

18

17

16

15

14

8129H-02

OE

A8 (Column Add. only)

A7

A6

A5

A4

Pin Names

A0–A8

RAS

CAS

WE

OE

I/O1–I/O8

V CC

V SS

Address Inputs (A8: Column Address only)

Row Address Strobe

Column Address Strobe

Write Enable

Output Enable

Data Input, Output

+5V Supply

0V Supply

Absolute Maximum Ratings*

Ambient Temperature

Under Bias .............................. –10°C to +80°C

Storage Temperature (plastic) ..... –55°C to +125°C

Voltage Relative to VSS .................–1.0 V to +7.0 V

Data Output Current ..................................... 50 mA

Power Dissipation .......................................... 1.0 W

*Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

Capacitance*

TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V

Symbol

Parameter

Typ. Max.

CIN1

Address Input

3

4

CIN2

RAS, CAS, WE, OE

4

5

COUT

Data Input/Output

5

7

* Note: Capacitance is sampled and not 100% tested

Unit

pF

pF

pF

V53C8129H Rev. 1.3 July 1997

2

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