P3C1256-12JC 查看數據表（PDF） - Performance Semiconductor

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P3C1256-12JC

HIGH SPEED 32K x 8 3.3V STATIC CMOS RAM

Performance Semiconductor 

P3C1256

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(6)

ADDRESS

CE

tWC (9)

tAS

tCW

tAW

tAH

WE

DATA IN

DATA OUT(6)

tWP

tDW

tDH

DATA VALID

HIGH IMPEDANCE

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

Mode

CE OE WE I/O Power

Standby

H X X High Z Standby

Standby

X X X High Z Standby

DOUT Disabled L H H High Z Active

Read

L

L

H

DOUT

Active

Write

L X L High Z Active

DOUT

350Ω

+3.3V

320Ω

30pF* (5pF* for tHZ, tLZ, tOHZ,

tOLZ, tWZ and tOW)

D OUT

R TH = 167.2 Ω

VTH = 1.72V

30pF* (5pF* for tHZ, tLZ, tOHZ,

tOLZ, tWZ and TOW)

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P3C1256, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads that

cause supply bounce must be avoided by bringing the VCC and ground

planes directly up to the contactor fingers. A 0.01 µF high frequency

capacitor is also required between V and ground. To avoid signal

CC

Figure 2. Thevenin Equivalent

reflections, proper termination must be used; for example, a 50Ω test

environment should be terminated into a 50Ω load with 1.73V (Thevenin

Voltage) at the comparator input, and a 116Ω resistor must be used in

series with DOUT to match 166Ω (Thevenin Resistance).

138

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