SPT561AIJ 查看數據表（PDF） - Signal Processing Technologies
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SPT561AIJ Datasheet PDF : 12 Pages
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SUMMARY DESIGN EQUATIONS AND DEFINITIONS
+VCC (+15)
Rf = (G + 1) Ro − AvRi
Rg
=
Rf − Ro
Av −1
Cx =
1
Ro
− 0.08
300
1−
2
Rg
Rf – Feedback resistor
from output to inverting
input
Rg – Gain setting
resistor from inverting
input to ground
Cx – External
compensation capacitor
from output to
pin 19 (in pF)
Where:
Ro – Desired equivalent output impedance
Av – Non-inverting input to output voltage
gain with no load
G – Internal current gain from inverting input
to output = 10 ±1%
Ri – Internal inverting input impedance = 14Ω ±%5
Rs – Non-inverting input termination resistor
RL – Load resistor
AL – Voltage gain from non-inverting input to
load resistor
SPT561 Description of Operation
Looking at the circuit of Figure 1 (the topology and
resistor values used in setting the data sheet specifica-
tions), the SPT561 appears to bear a strong external
resemblance to a classical op amp. As shown in the
simplified block diagram of Figure 2, however, it differs in
several key areas. Principally, the error signal is a
current into the inverting input (current feedback) and the
forward gain from this current to the output is relatively
low, but very well controlled, current gain. The SPT561
has been intentionally designed to have a low internal
gain and a current mode output in order that an equivalent
output impedance can be achieved without the series
matching resistor more commonly required of low output
impedance op amps. Many of the benefits of a high loop
gain have, however, been retained through a very careful
control of the SPT561’s internal characteristics.
The feedback and gain setting resistors determine both
the output impedance and the gain. Rf predominately
sets the output impedance (Ro), while Rg predominately
determines the no load gain (Av). solving for the required
Rf and Rg, given a desired Ro and Av, yields the design
equations shown below. Conversely, given an Rf and Rg,
the performance equations show that both Rf and Rg play
a part in setting Ro and Av. Independent Ro and Av
adjustment would be possible if the inverting input imped-
ance (Ri) were 0 but, with Ri = 14Ω as shown in the
specification listing, independent gain and output imped-
ance setting is not directly possible.
+
6.8µF
.1µF
Cx
Vi
(Pi)
Rs
50Ω
8
4 19
+
10.5pF
Ro
SPT561 23
18 -
Vo
RL (Po)
5,10,15,
50Ω
21
20
Rf
410Ω
Rg
Resistor Values
shown result in:
40Ω
Ro = 50Ω
.1µF
+ 6.8µF Av = +10
(no-load gain)
-VCC (-15)
AL = +5 [14dB]
(gain to 50Ω load)
Figure 1: Test Circuit
Design Equations
Rf = (G + 1) Ro − AvRi
Rg
=
Rf − Ro
Av −1
Performance Equations
Ro
=
Rf
+
Ri
1+
Rf
Rg
G + 1+ Ri
Rg
Av
= 1+
Rf
Rg
G − Ri
Rf
G
+
1+
Ri
Rg
Where:
G ≡ forward current gain
(=10)
Ri ≡ inverting node input
resistance (=14Ω)
Ro ≡ desired output
impedance
Av ≡ desired non-
inverting voltage
gain with no load
Simplified Circuit Description
Looking at the SPT561’s simplified schematic in Figure 2, the
amplifier’s operation may be described. Going from the non-
inverting input at pin 8 to the inverting input at pin 18,
transistors Q1 – Q4 act as an open loop unity gain buffer
forcing the inverting node voltage to follow the non-inverting
voltage input.
Transistors Q3 and Q4 also act as a low impedance (14Ω
looking into pin 18) path for the feedback error current. This
current, (ierr), flows through those transistors into a very well
defined current mirror having a gain of 10 from this error
current to the output. The current mirror outputs act as the
amplifier output.
The input stage bias currents are supply voltage independent.
Since these set the bias level for the whole part, relatively
constant performance over supply voltage is achieved. A
current sense in the error current leg of the 10X current mirror
SPT561
6
10/9/98
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