MAX9586(2007) 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

比赛名单

MAX9586
(Rev.:2007)

Single, Dual, Triple, and Quad Standard-Definition Video Filter Amplifiers with AC-Coupled Input Buffers

Maxim Integrated 

Single, Dual, Triple, and Quad Standard-Definition

Video Filter Amplifiers with AC-Coupled Input Buffers

ABSOLUTE MAXIMUM RATINGS

VDD to GND ..............................................................-0.3V to +4V

IN_ to GND ...............................................................-0.3V to +4V

SHDN to GND...........................................................-0.3V to +4V

OUT_ Short Circuit Duration to VDD, GND .................Continuous

Continuous Input Current

IN_, SHDN ....................................................................±20mA

Continuous Power Dissipation (TA = +70°C)

5-Pin Thin SOT23 (derate 9.1mW/°C above +70°C) ....727mW

6-Pin Thin SOT23 (derate 9.1mW/°C above +70°C) ....727mW

8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW

10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature ......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = 3.3V, GND = 0V, VRL = no load, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS

Supply Voltage Range

Supply Current

Sync-Tip Clamp Level

Input Voltage Range

VDD

IDD

VCLP

VIN

Guaranteed by PSRR

Per channel

Sync-tip clamp

VDD = 2.7V, sync-tip clamp

input

Guaranteed by DC VDD = 2.7V, bias input

voltage gain

VDD = 3V, sync-tip clamp input

2.7

0.24

4.25

3.6

V

8

mA

0.41

V

1.05

1.05

1.2

VP-P

VDD = 3V, bias input

1.2

Sync Crush

Sync-tip clamp, percentage reduction in sync pulse

(0.3VP-P), guaranteed by input clamping current

measurement, measured at input

2

%

Input Clamping Current

Maximum Input Source

Resistance

Sync-tip clamp

1

2

µA

300

Ω

Bias Voltage

Input Resistance

VBIAS

Bias circuit

Bias circuit

0.40 0.50 0.62

V

11

kΩ

VDD = 2.7V, VIN = VCLP to

(VCLP + 1.05V)

VDD = 3V, VIN = VCLP to

(VCLP + 1.2V)

DC Voltage Gain (Note 2)

AV

RL = 150Ω to GND

VDD = 2.7V, VIN = VBIAS

±0.525V

1.95 2.00 2.04

1.95 2.00 2.04

V/V

1.95 2.00 2.04

DC Gain Matching

Output Level

VDD = 3V, VIN = VBIAS

±0.600V

Guaranteed by DC voltage gain

Measured at VOUT,

IN_ = 0.1µF to GND,

RL = 150Ω to GND

Sync-tip clamp

Bias circuit

1.95 2.00 2.04

-2

0

+2

%

0.2

0.3

0.4

V

1.3

2 _______________________________________________________________________________________

Share Link: