TDA7438D013TR 查看數據表（PDF） - STMicroelectronics

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TDA7438D013TR

THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR

STMicroelectronics 

TDA7438

Figure 15. Acknowledge on the I2CBUS

SCL

1

2

3

7

8

9

SDA

START

MSB

D99AU1033

ACKNOWLEDGMENT

FROM RECEIVER

5 SOFTWARE SPECIFICATION

Interface Protocol

The interface protocol comprises:

■ A start condition (S)

■ A chip address byte, containing the TDA7438 address

■ A subaddress bytes

■ A sequence of data (N byte + acknowledge)

Figure 16.

CHIP ADDRESS

SUBADDRESS

DATA 1 to DATA n

MSB

LSB

MSB

S 1 0 0 0 1 0 0 0 ACK X X X B

D96AU420

ACK = Acknowledge

S = Start

P = Stop

A = Address

B = Auto Increment

LSB

MSB

DATA

ACK

DATA

LSB

ACK P

5.1 EXAMPLES

5.1.1 No Incremental Bus

The TDA7438 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incre-

mental bus), N-data (all these data concern the subaddress selected), a stop condition.

Figure 17.

CHIP ADDRESS

SUBADDRESS

DATA

MSB

LSB

MSB

LSB

MSB

S 1 0 0 0 1 0 0 0 ACK X X X 0 D3 D2 D1 D0 ACK

D96AU421

DATA

LSB

ACK P

5.1.2 Incremental Bus

The TDA7438 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremen-

tal bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from

"XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA

2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition

9/19

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