FS6146 查看數據表（PDF） - AMI Semiconductor
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FS6146 Datasheet PDF : 6 Pages
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FS6146
VCXO Clock Generator IC
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
IDD
fXTAL = 13.5MHz; CL = 10pF
20
Voltage Controlled Crystal Oscillator - VDD=5.0V
Crystal Loading Capacitance
CL(xtal)
As seen by a crystal connected to XIN and
XOUT (@ VXTUNE = 1.65V)
14
Crystal Resonator Motional Capacitance
C1(xtal)
AT cut
25
VCXO Tuning Range
fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal) = 25fF
300
VCXO Tuning Characteristic
Note: positive ∆F for positive ∆V
100
Crystal Drive Level
RXTAL=20Ω; CL(xtal) = 14pF
200
Clock Outputs (CLKA, CLKB) - VDDO=3.3V
High-Level Output Source Current *
IOH
VO = 2.0V
-40
Low-Level Output Sink Current *
IOL
VO = 0.4V
17
Output Impedance *
zOH
VO = 0.1VDD; output driving high
25
zOL
VO = 0.1VDD; output driving low
25
Short Circuit Source Current *
IOSH
VO = 0V; shorted for 30s, max.
-55
Short Circuit Sink Current *
IOSL
VO = 5V; shorted for 30s, max.
55
mA
pF
fF
ppm
ppm/V
uW
mA
mA
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Overall
VCXO Stabilization Time *
PLL Stabilization Time *
Output Frequency Synthesis Error
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ)) *
Rise Time *
Fall Time *
tVCXOSTB
tPLLSTB
tj(∆P)
tj(LT)
tr
tf
From power valid
From VCXO stable
(unless otherwise noted in Frequency Table)
Ratio of high pulse width (as measured from rising edge
to next falling edge at VDD/2) to one clock period
From rising edge to next rising edge at
VDD/2, CL = 10pF
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF
VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF
10
ms
500
us
0
ppm
45
55
%
300
ps
150
ps
ns
ns
4
ISO9001
2.27.02
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