GS880Z18AT-250 查看數據表（PDF） - Giga Semiconductor

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GS880Z18AT-250

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

Pipeline Mode Read/Write Cycle Timing

GS880Z18/36AT-250/225/200/166/150/133

CK

CKE

E*

ADV

W

Bn

1

2

3

4

5

6

7

8

9

10

tS tH

tS tH

tKH tKL tKC

tS tH

tS tH

tS tH

tS tH

A0–An

DQA–DQD

G

A1

A2

A3

A4

A5

A6

A7

D(A1)

tKQ

tKQLZ

tGLQV tKHQZ

tKQHZ

D

D(A2) (A2+1)

Q(A3)

Q(A4)

Q

(A4+1)

D(A5)

Q(A6)

tS tH

tOEHZ

tKQX

tOELZ

COMMAND

Write

D(A1)

Write BURST Read

D(A2) Write Q(A3)

D(A2+1)

Read BURST

Q(A4) Read

Q(A4+1)

Write Read

D(A5) Q(A6)

Write DESELECT

D(A7)

DON’T CARE

UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.02 9/2002

19/25

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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