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CD4028

BCD-to-Decimal Decoder

Fairchild Semiconductor 

October 1987

Revised January 1999

CD4028BC

BCD-to-Decimal Decoder

General Description

The CD4028BC is a BCD-to-decimal or binary-to-octal

decoder consisting of 4 inputs, decoding logic gates, and

10 output buffers. A BCD code applied to the 4 inputs, A, B,

C, and D, results in a high level at the selected 1-of-10 dec-

imal decoded outputs. Similarly, a 3-bit binary code applied

to inputs A, B, and C is decoded in octal at outputs 0–7. A

high level signal at the D input inhibits octal decoding and

causes outputs 0–7 to go LOW.

All inputs are protected against static discharge damage by

diode clamps to VDD and VSS.

Features

s Wide supply voltage range: 3.0V to 15V

s High noise immunity: 0.45 VDD (typ.)

s Low power TTL compatibility: fan out of 2 driving 74L

or 1 driving 74LS

s Low power

s Glitch free outputs

s “Positive logic” on inputs and outputs

Applications

• Code conversion

• Address decoding

• Indicator-tube decoder

Ordering Code:

Order Number Package Number

Package Description

CD4028BCM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

CD4028BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

© 1999 Fairchild Semiconductor Corporation DS005959.prf

www.fairchildsemi.com

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