CD4046BC 查看數據表（PDF） - Fairchild Semiconductor

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CD4046BC

Micropower Phase-Locked Loop

Fairchild Semiconductor 

Design Information

This information is a guide for approximating the value of

external components for the CD4046B in a phase-locked-

loop system. The selected external components must be

within the following ranges: R1, R2 ≥ 10 kΩ, RS ≥ 10 kΩ,

C1 ≥ 50 pF.

In addition to the given design information, refer to Figure

5, Figure 6, Figure 7 for R1, R2 and C1 component selec-

tions.

Characteristics

VCO Frequency

Using Phase Comparator I

VCO Without Offset

VCO With Offset

R2 = ∞

Using Phase Comparator II

VCO Without Offset

VCO With Offset

R2 = ∞

For No Signal Input

Frequency Lock

Range, 2 fL

Frequency Capture

Range, 2 fC

VCO in PLL system will adjust

VCO in PLL system will adjust to

to center frequency, fo

lowest operating frequency, fmin

2 fL = full VCO frequency range

2 fL = fmax − fmin

Loop Filter Component

Selection

For 2 fC, see Ref.

Phase Angle Between

Single and Comparator

Locks on Harmonics

of Center Frequency

Signal Input Noise

Rejection

90° at center frequency (fo), approximating

0° and 180° at ends of lock range (2 fL)

Yes

High

fC = fL

Always 0° in lock

No

Low

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