CY2305SXC-1(2008) 查看數據表（PDF） - Cypress Semiconductor

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CY2305SXC-1
(Rev.:2008)

Low-Cost 3.3V Zero Delay Buffer

Cypress Semiconductor 

Pinouts

Table 1. Pin Description for CY2305

Pin

Signal

1

REF[1]

2

CLK2[2]

3

CLK1[2]

4

GND

5

CLK3[2]

6

VDD

7

CLK4[2]

8

CLKOUT[2]

Figure 1. Pin Diagram - CY2305

REF 1

CLK2 2

CLK1 3

GND 4

8 CLKOUT

7 CLK4

6 VDD

5 CLK3

Description

Input reference frequency, 5V-tolerant input

Buffered clock output

Buffered clock output

Ground

Buffered clock output

3.3V supply

Buffered clock output

Buffered clock output, internal feedback on this pin

Table 2. Pin Description for CY2309

Pin

Signal

1

REF[1]

2

CLKA1[2]

3

CLKA2[2]

4

VDD

5

GND

6

CLKB1[2]

7

CLKB2[2]

8

S2[3]

9

S1[3]

10

CLKB3[2]

11

CLKB4[2]

12

GND

Notes

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

Document #: 38-07140 Rev. *I

Figure 2. Pin Diagram - CY2309

REF 1

CLKA1 2

CLKA2 3

VDD

4

GND 5

CLKB1 6

CLKB2 7

S2 8

16 CLKOUT

15 CLKA4

14 CLKA3

13

VDD

12 GND

11 CLKB4

10 CLKB3

9 S1

Description

Input reference frequency, 5V-tolerant input

Buffered clock output, Bank A

Buffered clock output, Bank A

3.3V supply

Ground

Buffered clock output, Bank B

Buffered clock output, Bank B

Select input, bit 2

Select input, bit 1

Buffered clock output, Bank B

Buffered clock output, Bank B

Ground

CY2305

CY2309

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