CY7C43686AV-10 查看數據表（PDF） - Cypress Semiconductor

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产品描述 (功能)

比赛名单

CY7C43686AV-10

3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO

Cypress Semiconductor 

CY7C43646AV

CY7C43666AV

CY7C43686AV

Pin Definitions (continued)

Signal Name Description

PRS2

FIFO2 Partial

Reset

RENB

RT1

RT2

SIZEB

Port B Read

Enable

FIFO1

Retransmit

FIFO2

Retransmit

Bus Size Select

SIZEC

Bus Size Select

SPM

W/RA

WENC

Serial

Programming

Port A

Write/Read

Select

Port C Write

Enable

I/O

Function

I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location

of memory and sets the Port A output register to all zeroes. During Partial Reset,

the currently selected bus size, endian arrangement, programming method (serial or

parallel), and programmable flag settings are all retained.

I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read data on

Port B.

I A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing

the Read pointer back to location zero. The user will still need to perform Read opera-

tions to retransmit the data. Retransmit function applies to CY Standard mode only.

I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing

the Read pointer back to location zero. The user will still need to perform Read opera-

tions to retransmit the data. Retransmit function applies to CY Standard mode only.

I A HIGH on this pin selects byte bus (9-bit) size on Port B. A LOW on this pin selects

word (18-bit) bus size. SIZEB works with BE to select the bus size and endian

arrangement for Port B. The level of SIZEB must be static throughout device operation.

I A HIGH on this pin selects byte bus (9-bit) size on Port C. A LOW on this pin selects

word (18-bit) bus size. SIZEC works with BE to select the bus size and endian

arrangement for Port C. The level of SIZEC must be static throughout device operation.

I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on

this pin selects parallel programming or default offsets (8, 16, or 64).

I A HIGH selects a Write operation and a LOW selects a Read operation on Port A

for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the HIGH impedance

state when W/RA is HIGH.

I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on

Port C.

Document #: 38-06026 Rev. *C

Page 6 of 40

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