GS8322Z18 查看數據表（PDF） - Giga Semiconductor

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GS8322Z18

36Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72 209-Bump BGA Pin Description

Symbol

A0, A1

An

DQA

DQB

DQC

DQD

DQE

DQF

DQG

DQH

BA, BB

BC,BD

BE, BF, BG,BH

NC

CK

E1

E3

E2

G

ADV

ZZ

FT

LBO

MCH

MCH

MCL

W

Type

I

I

I/O

I

I

I

—

I

I

I

I

I

I

I

I

I

I

I

I

ZQ

I

CKE

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQA, DQB I/Os; active low

Byte Write Enable for DQC, DQD I/Os; active low

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

No Connect

Clock Input Signal; active high

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Must Connect High

Must Connect High

Must Connect Low

Write Enable; active low

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive],

High = High Impedance [Low Drive]

Clock Enable; active low

Rev: 1.04 11/2004

3/38

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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