HEC4040BN 查看數據表（PDF） - Philips Electronics
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HEC4040BN Datasheet PDF : 5 Pages
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Philips Semiconductors
12-stage binary counter
Product specification
HEF4040B
MSI
VDD
V
SYMBOL MIN. TYP. MAX.
Minimum clock
pulse width; HIGH
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
5
10 tWCPH
15
5
10 tWMRH
15
5
10 tRMR
15
5
10 fmax
15
50 25
30 15
20 10
40 20
30 15
20 10
40 20
30 15
20 10
10 20
15 30
25 50
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
Note
1. For other loads than 50 pF at the nth output, use the slope given.
TYPICAL EXTRAPOLATION
FORMULA
see also waveforms
Fig.4
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
400 fi + ∑ (foCL) × VDD2
where
10
2 000 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
5 200 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
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