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IS1002 查看數據表(PDF) - Unspecified

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IS1002 Datasheet PDF : 13 Pages
First Prev 11 12 13
創傑科技股份有限公司
Integrated System Solution Corp.
IS1002
Bluetooth Baseband Controller
7.11 Processor Memory Map1
The addressable memory space of the 8051 Turbo processor consists of a 64 kByte
program space and a 64 kByte data space. The 64 kByte program space is mapped onto
two pages in a larger 128 kByte memory space. This 128 kByte space may be physically
implemented in a Flash or ROM device. The 64 kByte data space contains a single-port
RAM, and the register bank. The maximum size of each memory component is as follows.
Memory
Component
program memory
data segment 1
register segment
data segment 2
reserved
Physical
Device
Flash or ROM
Maximum
Size
128 kBytes
single port
RAM
register bank
Common
memory
32 kBytes
16 kBytes
13 kBytes
Address range
page 0: 0000h – ffffh
page 1: 0000h – ffffh
0000h – 7fffh
8000h – bfffh
c000h – f3ffh
f400h – ffffh
7.12 Miscellaneous (Watchdog Timer, PLL, and Clock Divider)
System related functions such as watchdog timer, Endian control, and interrupt vectors are
also provided.
The purpose of the watchdog timer is to provide a reset to CPU in case when the CPU
fails to service the watchdog timer in a pre-defined (programmable) period. In this
situation, the CPU will be reset, and a flag will be set to indicate that the reset was due to a
watchdog “timeout”. In addition, it also provides resets to the other modules in Bluetooth
baseband.
The build in PLL circuit will generate the required system clock of 48MHz, 36MHz or
24MHz from the oscillator clock. The clock divider will provide fixed frequencies of 12 MHz,
8KHz…for Bluetooth core and other peripheral hardware based on the input system clock
of 48MHz, 36MHz, or 24MHz. All system clocks are 50% duty cycle.
1 Additional memory spaces such as TX/RX buffer, USB/UART buffer are not addressable by 8051. Those
special memory modules are controlled indirectly by 8051 via data router.
Preliminary Datasheet
page 11
Released date: July 2004
Revision 0.9

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