IS61C3216-20K 查看數據表（PDF） - Integrated Circuit Solution Inc

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IS61C3216-20K

32K x 16 HIGH-SPEED CMOS STATIC RAM

Integrated Circuit Solution Inc 

IS61C3216

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol

Parameter

-10

Min. Max.

-12

Min. Max.

-15

Min. Max.

-20

Min. Max. Unit

tWC

Write Cycle Time

tSCE

CE to Write End

10 —

9—

12 —

10 —

15 —

11 —

20 — ns

12 — ns

tAW

Address Setup Time

to Write End

9—

10 —

11 —

12 — ns

tHA

Address Hold from Write End

1—

1—

1—

1 — ns

tSA

Address Setup Time

tPWB

LB, UB Valid to End of Write

tPWE

WE Pulse Width

0—

9—

7—

0—

10 —

8—

0—

11 —

10 —

0 — ns

12 — ns

11 — ns

tSD

Data Setup to Write End

5—

6—

7—

8 — ns

tHD

t (2)

HZWE

t (2)

LZWE

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

0—

—5

1—

0—

—6

1—

0—

—7

1—

0 — ns

— 8 ns

1 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the write.

6

Integrated Circuit Solution Inc.

SR008-0B

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