5962-9054302MQA(1997) 查看數據表（PDF） - Intersil

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产品描述 (功能)

生产厂家

5962-9054302MQA
(Rev.:1997)

CMOS High Performance Programmable DMA Controller

Intersil 

Timing Waveforms

82C37A

CS

IOW

A0 - A3

DB0 - DB7

TCWL

(43)

TAWL

(42)

TWWS

(55)

INPUT VALID

TDW

(44)

INPUT VALID

TWC (53)

TWA (52)

TWD (54)

FIGURE 8. SLAVE MODE WRITE

NOTE: Successive WRITE accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must

be allowed before executing a WRITE access after a READ access.

CS

A0 - A3

IOR

DB0 -DB7

TAR

(41)

ADDRESS MUST BE VALID

TRW

(51)

TRDE

(46)

TRA (45)

TRDF

(47)

DATA OUT VALID

FIGURE 9. SLAVE MODE READ

NOTE: Successive READ accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must

be allowed before executing a READ access after a WRITE access.

4-209

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