MAX17021 查看數據表（PDF） - Maxim Integrated

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MAX17021

Dual-Phase, Quick-PWM Controllers for IMVP-6+/IMVP-6.5 CPU Core Power Supplies

Maxim Integrated 

Dual-Phase, Quick-PWM Controllers for

IMVP-6+/IMVP-6.5 CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1

= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:

VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

Quiescent Supply Current

(V3P3)

SYMBOL

I3P3

CONDITIONS

Measured at V3P3, FB forced within the CLKEN

power-good window

MIN TYP MAX UNITS

2

4

μA

Shutdown Supply Current

(VCC)

ICC,SDN Measured at VCC, SHDN = GND, TA = +25°C

0.01

1

μA

Shutdown Supply Current

(VDD)

IDD,SDN Measured at VDD, SHDN = GND, TA = +25°C

0.01

1

μA

Shutdown Supply Current

(V3P3)

I3P3,SDN Measured at V3P3, SHDN = GND, TA = +25°C

0.01

1

μA

FAULT PROTECTION

Skip mode after output reaches the regulation

voltage or PWM mode; measured at FB with

respect to the voltage target set by the VID code;

250

300

350

mV

Output Overvoltage-

see Table 4.

Protection Threshold

(MAX17021/MAX17082 Only)

VOVP

Soft-start, soft-shutdown, skip IMVP-6.5

mode, and output have not

(MAX17082)

1.45 1.50 1.55

reached the regulation

voltage; measured at FB

IMVP-6+

(MAX17021)

V

1.75 1.80 1.85

Minimum OVP threshold; measured at FB

0.8

Output Overvoltage-

Propagation Delay

(MAX17021/MAX17082 Only)

tOVP

FB forced 25mV above trip threshold

10

μs

Output Undervoltage-

Protection Threshold

Measured at FB with respect to the voltage target

VUVP

set by the VID code; see Table 4

-450 -400 -350 mV

Output Undervoltage-

Propagation Delay

CLKEN Startup Delay and

Boot Time Period

PWRGD Startup Delay

tUVP

tBOOT

FB forced 25mV below trip threshold

Measured from the time when FB reaches the

boot target voltage (Note 2)

Measured at startup from the time when CLKEN

goes low

10

μs

20

60 100

μs

3

6.5

10

ms

CLKEN and PWRGD

Threshold

Lower threshold,

Measured at FB with respect falling edge

-350 -300 -250

to the voltage target set by

the VID code; see Table 4,

(undervoltage)

Upper threshold,

mV

20mV hysteresis (typ)

rising edge

+150 +200 +250

(overvoltage)

CLKEN and PWRGD Delay

PHASEGD Delay

FB forced 25mV outside the PWRGD trip

threshold s

V(CCI,FB) forced 25mV outside trip thresholds

10

μs

10

μs

4 _______________________________________________________________________________________

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