MAX2038CCQD 查看數據表（PDF） - Maxim Integrated
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MAX2038CCQD Datasheet PDF : 24 Pages
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Ultrasound VGA Integrated
with CW Octal Mixer
AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE (continued)
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0,
CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low
impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SERIAL SHIFT REGISTER
Serial Shift Register
Programming Rate
Minimum Data Set-Up Time
Minimum Data Hold Time
Minimum Data Clock Time
Minimum Data Clock Pulse Width
High
tDSU
tHLD
tDCLK
tDCLKPWH
10
MHz
30
ns
2
ns
100
ns
30
ns
Minimum Data Clock Pulse Width
Low
Minimum Load Line
Minimum Load Line High to
Mixer Clock On
tDCLKPWL
tLD
tMIXCLK
30
ns
30
ns
30
ns
Minimum Data Clock to Load
Line High
tCLH
30
ns
Note 2: Specifications at TA = +25°C and TA = +70°C are guaranteed by production test. Specifications at TA = 0°C are guaran-
teed by design and characterization.
Note 3:
Note 4:
Note 5:
Noise performance of the device is dependent on the noise contribution from the supply to VREF. Use a low-noise supply for
VREF. VCC and VREF can be connected together to share the same supply voltage if the supply for VCC exhibits low noise.
Total on-chip power dissipation is calculated as PDISS = VCC x ICC + VREF x IREF + [11V - (IMIX/4) x 115] x IMIX.
Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes there to be a period of time (related to the RC time constant) when the DC level on the
chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not exceed both the
logic thresholds required for proper operation. This problem associated with AC-coupling would cause an inability to
ensure synchronization among beam-forming channels. The LVDS signal is terminated differentially with an external 100Ω
resistor on the board.
Note 6: External 100Ω resistor terminates the LVDS differential signal path.
Note 7: The mixer common-mode current (3.25mA/channel) is specified as the common-mode current in each of the differential
mixer outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+, CW_IOUT-).
Note 8: Specification guaranteed only for DOUT driving DIN of the next device in a daisy-chain fashion.
Note 9: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive and
a switching network is recommended as shown in the Applications Information section.
Note 10: See the Ultrasound-Specific IMD3 Specification in the Applications Information section.
Note 11: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 12: Channel-to-channel gain-and-phase matching measured on 30 pieces during engineering characterization at room tem-
perature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the
angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the
phase variation.
Note 13: Transconductance is defined as the quadrature summing of the CW differential output current at baseband divided by the
mixer’s input voltage.
6 _______________________________________________________________________________________
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