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MAX4040ESA 查看數據表(PDF) - Maxim Integrated

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产品描述 (功能)
比赛名单
MAX4040ESA Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Single/Dual/Quad, Low-Cost, SOT23,
Micropower, Rail-to-Rail I/O Op Amps
______________________________________________________________Pin Description
MAX4040
SOT23-5 SO/µMAX
PIN
MAX4041 MAX4042
MAX4043
µMAX SO
1
6
6
NAME
MAX4044
OUT
2
4
4
3
3
3
4
2
2
5
7
7
1, 5, 8
1, 5
4
4
4
11
VEE
IN+
IN-
8
10
14
4
VCC
5, 7,
8, 10
N.C.
8
SHDN
FUNCTION
Amplifier Output. High impedance
when in shutdown mode.
Negative Supply. Tie to ground for
single-supply operation.
Noninverting Input
Inverting Input
Positive Supply
No Connection. Not internally con-
nected.
Shutdown Input. Drive high, or tie to
VCC for normal operation. Drive to VEE
to place device in shutdown mode.
1, 7
1, 9 1, 13
1, 7
OUTA, Outputs for Amplifiers A and B. High
OUTB impedance when in shutdown mode.
2, 6
2, 8 2, 12
2, 6
INA-,
INB-
Inverting Inputs to Amplifiers A and B
3, 5
3, 7 3, 11
3, 5
INA+,
INB+
Noninverting Inputs to Amplifiers A
and B
Shutdown Inputs for Amplifiers A
5, 6 6, 9
SHDNA, and B. Drive high, or tie to VCC for
SHDNB normal operation. Drive to VEE to
place device in shutdown mode.
8, 14
OUTC,
OUTD
Outputs for Amplifiers C and D
9, 13
INC-,
IND-
Inverting Inputs to Amplifiers C and D
10, 12
INC+,
IND+
Noninverting Inputs to Amplifiers C
and D
_______________Detailed Description
Rail-to-Rail Input Stage
The MAX4040–MAX4044 have rail-to-rail inputs and
rail-to-rail output stages that are specifically designed
for low-voltage, single-supply operation. The input
stage consists of separate NPN and PNP differential
stages, which operate together to provide a common-
mode range extending to both supply rails. The
crossover region of these two pairs occurs halfway
between VCC and VEE. The input offset voltage is typi-
cally 200µV. Low operating supply voltage, low supply
current, rail-to-rail common-mode input range, and rail-
to-rail outputs make this family of operational amplifiers
an excellent choice for precision or general-purpose,
low-voltage battery-powered systems.
Since the input stage consists of NPN and PNP pairs,
the input bias current changes polarity as the common-
mode voltage passes through the crossover region.
Match the effective impedance seen by each input to
reduce the offset error caused by input bias currents
flowing through external source impedances (Figures
1a and 1b). The combination of high source impedance
plus input capacitance (amplifier input capacitance
plus stray capacitance) creates a parasitic pole that
produces an underdamped signal response. Reducing
input capacitance or placing a small capacitor across
the feedback resistor improves response in this case.
8 _______________________________________________________________________________________

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