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MK5027(2003) 查看數據表(PDF) - STMicroelectronics

零件编号
产品描述 (功能)
比赛名单
MK5027
(Rev.:2003)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
MK5027 Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MK5027
MK5027 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Temperature under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground
Power Dissipation
–25°C to +100°C
–65°C to +150°C
–0.5V to VCC +0.5V
0.50W
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the above device. This is a stress rating only
and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.
DC CHARACTERISTICS
TA=0 °C to 70 °C, VCC = +5V ±5 percent unless otherwise specified.
Symbol
VIL
VIH
VOL
VOH
IIL
ICC
@ IOL = 3.2 mA
@ IOH= -0.4 mA
@ VIN = 0.4 to VCC
@ TSCT = 100 ns
CAPACITANCE
f = 1MHz
Parameter
Symbol
CIN
COUT
CIO
Parameter
Capacitance on Input pins
Capacitance on Output Pins
Capacitance on I/O pins
Min.
-0.5
+2.0
+2.4
Typ.
50
Max.
+0.8
VCC +0.5
+0.5
+10
Units
V
V
V
V
mA
µA
Min.
Typ.
Max.
10
10
20
Units
pF
pF
pF
AC TIMING SPECIFICATIONS
TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified.
No Signal Symbol
1 SYSCLK
2 SYSCLK
3 SYSCLK
4 SYSCLK
5 SYSCLK
6 TCLK
7 TCLK
8 TCLK
9 TCLK
10 TCLK
11 TD
TSCT
TSCL
TSCH
TSCR
TSCF
TTCT
TTCL
TTCH
TTCR
TTCF
TTDP
12 TD
TTDH
Parameter
SYSCLK period
SYSCLK low time
SYSCLK high time
Rise time of SYSCLK
Fall time of SYSCLK
TCLK period
TCLK low time
TCLK high time
Rise time of TCLK
Fall time of TCLK
TD data propagation delay after the
falling edge of TCLK
TD data hold time after the falling edge
of TCLK
Test
Condition
CL = 50 pF
CL = 50 pF
Min.
100
45
45
0
0
140
63
63
0
0
5
Typ.
Max. Units
20000 ns
ns
ns
8
ns
8
ns
ns
ns
ns
8
ns
8
ns
40 ns
ns
10/19

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