MK5027(2003) 查看數據表（PDF） - STMicroelectronics
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MK5027 Datasheet PDF : 19 Pages
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Figure 5A: TTL Output Load Diagram.
MK5027
Figure 5B: Open Drain Output Load Diagram.
FROM
OUTPUT
UNDER
TEST
TEST
POINT
CL
0.4 mA
Vcc
R1 = 1.2K
CR 1
CR1 - CR4 = 1N914 or EQUIV
CR 2
FROM
OUTPUT
UNDER
TEST
CR 3
CR 4
C = 50pF min @ 1 MHz
L
Vcc
R1 = 1.4K
C
L
NOTE: This load is used on all outputs except INTR, HOLD, READY.
NOTE: This load is used on open
drain outputs INTR, HOLD, READY.
Figure 6: MK5027 Serial Link Timing Diagram
RCLK
RD
TCLK
12
TD
13
15
14
16
21
19
20
18
6
8
7
10
11
TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES,
UNLESS OTHERWISE SPECIFIED:
"1"
"0"
OUTPUT
INPUT
FLOAT
2.0 V
2.0 V
10 %
O.8 V
O.8 V
90 %
17
9
13/19
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