MT5C6401 查看數據表（PDF） - Micron Technology
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MT5C6401 Datasheet PDF : 11 Pages
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AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
OBSOLETE 8/31/94
MT5C6401
64K x 1 SRAM
Q
255
+5V
480
30 pF
Q
255
+5V
480
5 pF
Fig. 1 OUTPUT LOAD
EQUIVALENT
Fig. 2 OUTPUT LOAD
EQUIVALENT
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < tRC/2.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is sampled.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tHZCE and tHZWE are specified with CL = 5pF as in
Fig. 2. Transition is measured ±500mV from steady
state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE and tHZWE is less than
tLZWE
8. ?W/E is HIGH for READ cycle.
9. Device is continuously selected. All chip enables are
held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Typical values are measured at 5V, 25°C and 15ns
cycle time.
14. Typical currents are measured at 25°C.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only)
DESCRIPTION
CONDITIONS
SYMBOL MIN
VCC for Retention Data
VDR
2
Data Retention Current
/C/E ≥ (Vcc -0.2V) VCC = 2V
VIN ≥ (VCC -0.2V)
or ≤ 0.2V
VCC = 3V
ICCDR
ICCDR
Chip Deselect to Data
tCDR
0
Retention Time
Operation Recovery Time
tR
tRC
TYP
MAX
130
300
210
400
UNITS
V
µA
µA
ns
NOTES
14
14
4
ns
4, 11
MT5C6401
REV. 12/93
7
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.
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