EXTERNAL DATA MEMORY WRITE CYCLE
MX10C805X
ALE
PSEN
WR
PORT 0
PORT 2
TLHLL
TWHLH
TLLWL
TWLWH
TAVLL
TLLAX
TQVWX
A0-A7 FROM RI OR DPL
TAVWL
TQVWH
DATA OUT
TWHQX
A0-A7 FROM
PCL
INSTR. IN
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION 0
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
1
2
3
4
5
6
7
8
TXLXL
TQVXH
TXHQX
0
1
2
TXHDV
TXHDX
VALID
VALID
VALID
3
4
5
VALID
VALID
VALID
6
VALID
7
VALID
P/N:PM0591
REV. 0.3, APR. 09, 1999
12