SAA3500H 查看數據表（PDF） - Philips Electronics

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产品描述 (功能)

比赛名单

SAA3500H

Digital audio broadcast channel decoder

Philips Electronics 

Philips Semiconductors

Digital audio broadcast channel decoder

Preliminary specification

SAA3500H

7 PINNING

SYMBOL PIN TYPE

DESCRIPTION

ADC

1 input analog-to-digital converter DC input

AIF

2 input analog-to-digital converter IF input

VSSA

ADE

3 ground analog supply ground

99 input analog-to-digital converter enable (active LOW)

VDDA

INP[0:9]

100 supply analog voltage supply (+3.3 V)

8 to 17 input 2048 kHz IF or baseband digital parallel input data (8 or 10 bits)

ADCLK

19 output analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW

IQS

20 input clock signal indicating I or Q baseband data if BYP = LOW;

signal for swapping I and Q data bytes if BYP = HIGH

BYP

21 input IF input stage bypass (active LOW)

FSI

22 input frame sync input (LOW indicates DAB null symbol detection)

FSO

23 output null detector/frame sync output (LOW indicates DAB null symbol position)

SLI

24 output AGC synchronization lock indicator (HIGH if synchronized)

AGC

25 output AGC level comparator output (HIGH if input sample > reference level, else LOW)

OSCI

4 input oscillator or system clock input, 24576 kHz

OSCO

5 output oscillator output

MCLK

41 output master clock output, 24576 kHz

VSS

7, 18, supply digital supply ground

26, 40,

60, 80

and 94

VDD

6, 28, supply digital voltage supply (+3.3 V)

42 and

79

TEST

92 input connect to ground for proper operation

OUT[0:7] 32 to 39 output baseband or channel impulse response output

OCLK

27 output output data clock (negative edge indicates new data)

OIQ

29 output output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW

OCIR

30 input output select: baseband if OCIR = HIGH, CIR if OCIR = LOW

OEN

31 input output enable (active LOW)

CFIC

51 output microcontroller interface signal indicating Fast Information Channel (FIC) processing

CMODE

CDATA

CCLK

52 input microcontroller interface mode input (only L3-bus)

53 I/O

microcontroller interface serial data I2C-bus or L3-bus (5 V tolerant)

54 input microcontroller interface clock input I2C-bus or L3-bus

RESET

55 input chip reset input (active LOW)

A[17:11] 62 to 68 output address outputs external RAM

A[10:0] 81 to 91 output address outputs external RAM

WR

61 output write data to RAM (active LOW)

RD

69 output read data from RAM (active LOW)

A17

70 output address bit 17 inverted for second RAM (128k × 8)

D[0:7]

71 to 78 I/O data input/output external RAM

2000 Jun 14

5

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