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NXP Semiconductors
SC18IS600
SPI to I2C-bus interface
CS
tSPIF
tSPILEAD
tSPIF
SCLK
(input)
MISO
(output)
tSPIOH
tSPIDV
tSPIA
not defined
TCLCL
tSCLKL
tSPIR
tSCLKH
tSPIOH
tSPIDV
slave MSB/LSB out
tSPIDSU tSPIDH
MOSI
(input)
MSB/LSB in
Fig 20. SPI slave timing (Mode 3)
tSPILAG
tSPIR
tSPIOH
tSPIDV
tSPIDSU
tSPIDIS
slave LSB/MSB out
tSPIDSU tSPIDH
LSB/MSB in
002aab797
SC18IS600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 20 November 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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