SP9500 查看數據表（PDF） - Signal Processing Technologies

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SP9500

12–Bit, Voltage Output D/A Converter

Signal Processing Technologies 

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device

at these or any other above those indicated in the operation

sections of the specifications below is not implied. Exposure to

absolute maximum rating conditions for extended periods of time

may affect reliability.

VDD - DGND .................................................................. -0.3V,+6.0V

VREF ................................................................................ DGND, VDD

AGND .......................................................................... DGND, VREF

DIN .................................................................................. DGND, VDD

Power Dissipation

Plastic DIP .......................................................................... 375mW

(derate 7mW/°C above +70°C)

Small Outline ...................................................................... 375mW

(derate 7mW/˚C above +70˚C)

SPECIFICATIONS

(Typical at 25˚C; TMIN ≤ TA ≤ TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

PARAMETER

MIN. TYP. MAX.

UNITS CONDITIONS

DIGITAL INPUTS

Logic Levels

VIH

VIL

2 Quad, Input Coding

2.4

0.8

Binary

Volts

Volts

REFERENCE INPUTS

VREF Voltage Range

AGND Voltage Range

Input Resistance

ANALOG OUTPUT

Gain

–B, –K

–A, –J

Initial Offset Bipolar

Voltage Range

Output Current

0.5

4.5

0.5

4.5

11

13.9

±0.5

±2.0

±1.0

±4.0

±1.0

±5.0

±0.25 ±3.0

0.5

4.5

±1.0

Volts

Volts

kΩ

Note 5

DIN = 1365; code dependent

LSB

LSB

LSB

LSB

Volts

mA

Note 3

Note 3

VREF = 4.5V; AGND = 0.5V

DIN = 0

STATIC PERFORMANCE

Resolution

Integral Linearity

–B, –K

–A, –J

Differential Linearity

–B, –K

–A, –J

Monotonicity

DYNAMIC PERFORMANCE

Settling Time

Small Signal

Full Scale

Slew Rate

Multiplying Bandwidth

STABILITY

Gain

Scale Zero

12

±0.25 ±0.5

±0.5

±1.0

±0.5

±0.25 ±0.75

±0.25 ±1.0

Guaranteed

1

7.5

0.6

1.4

15

15

Bits

LSB

Note 3

LSB

Note 3

LSB

VREF = 4.5V; AGND = 0.5V

LSB

LSB

µs

µs

V/µs

MHz

to 0.012%

to 0.012%, VOUT = 0.5 to 4.5V

ppm/˚C

ppm/˚C

tMIN to tMAX

tMIN to tMAX

SP9500DS/04

SP9500 12-Bit, Voltage Output D/A Converter

2

© Copyright 2000 Sipex Corporation

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