ST16C1450(2005) 查看數據表（PDF） - Exar Corporation
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ST16C1450 Datasheet PDF : 28 Pages
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AUGUST 2005
GENERAL DESCRIPTION
The ST16C1450 is a universal asynchronous
receiver and transmitter (UART). The 1450 is foot
print compatible to the SSI 73M1550 and SSI
73M2550 UART with one byte FIFO and higher
operating speed and lower access time. The 1450
provides enhanced UART functions with a modem
control interface, independent programmable baud
rate generators with clock rates to 1.5 Mbps. On
board status registers provide the user with error
indications and operational status. System interrupts
and modem control features may be tailored by
external software to meet specific user requirements.
An internal loop-back capability allows on board
diagnostics. The 1450 is available in a 28-pin PLCC
and 48-pin TQFP packages. The baud rate generator
can be configured for either crystal or external clock
input. The 48-pin TQFP package provides a buffered
reset output that can be controlled through user
software. The 1450 is fabricated in an advanced
CMOS process to achieve low drain power and high
speed requirements. The ST16C1450 is not
compatible with the industry standard 16450 and will
not work with the standard serial port driver in MS
Windows (see pages 12-13 for details). For a MS
Windows compatible UART, see the ST16C450.
ST16C1450
2.97V TO 5.5V UART
FEATURES
REV. 4.2.1
• Pin and functionally compatible to SSI 73M1550/
2550
• 1 byte Transmit FIFO (THR)
• 1 byte Receive FIFO with error tags (RHR)
• Four levels of prioritized interrupts
• Modem Control Signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
• Programmable character lengths (5, 6, 7, 8) with
even, odd or no parity
• Crystal or external clock input
• 1.5 Mbps Transmit/Receive operation (24 MHz)
with programmable clock control
• Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V)
• Software controllable reset output
• 2.97 to 5.5 Volt operation
APPLICATIONS
• Battery Operated Electronics
• Internet Appliances
• Handheld Terminal
• Personal Digital Assistants
• Cellular Phones DataPort
FIGURE 1. BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IO W #
CS#
INT
RESET
RST
Data Bus
Interface
THR
T ra n s m itte r
UART
Configuration
Regs
M odem Control Signals
Receiver
RHR
Baud Rate Generator
Crystal Osc/Buffer
TX
DTR#, RTS#
DSR#, CTS#,
CD#, RI#
RX
X T A L 1 /C L K
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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