UPD4564323 查看數據表（PDF） - NEC => Renesas Technology

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UPD4564323

64M-bit Synchronous DRAM 4-bank, LVTTL

NEC => Renesas Technology 

µPD4564323 for Rev. E

8. Address Bits of Bank-Select and Precharge

Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1

(Activate command)

BA1 BA0

00

01

10

11

Result

Select Bank A

“Activate” command

Select Bank B

“Activate” command

Select Bank C

“Activate” command

Select Bank D

“Activate” command

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1

(Precharge command)

A10 BA1 BA0 Result

0 0 0 Precharge Bank A

0 0 1 Precharge Bank B

0 1 0 Precharge Bank C

0 1 1 Precharge Bank D

1 x x Precharge All Banks

x : Don’t care

Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1

(/CAS strobes)

0

disables Auto-Precharge

(End of Burst)

1

enables Auto-Precharge

(End of Burst)

BA1 BA0

00

01

10

11

Result

enables Read/Write

commands for Bank A

enables Read/Write

commands for Bank B

enables Read/Write

commands for Bank C

enables Read/Write

commands for Bank D

22

Data Sheet M14376EJ2V0DS00

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