V53C16256H 查看數據表（PDF） - Mosel Vitelic, Corp
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V53C16256H Datasheet PDF : 19 Pages
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MOSEL VITELIC
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 ms is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C16256H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
V53C16256H
Table 1. V53C16256H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
CAS-Controlled Write
Cycle (Early Write)
WE-Controlled Write
Cycle (Late Write)
Read-Modify-Write
Cycles
Fast Page Mode Read
Fast Page Mode Write
Cycle (Early Write)
Fast Page Mode Read-
Modify-Write Cycle
RAS-only Refresh
CAS-before-RAS
Refresh Cycle
CAS-only Cycles
Data from Addressed
Memory Cell
High-Z
OE Controlled.
High OE = High-Z I/Os
Data from Addressed
Memory Cell
Data from Addressed
Memory Cell
High-Z
Data from Addressed
Memory Cell
High-Z
Data remains as in
previous cycle
High-Z
V53C16256H Rev. 2.3 June 1998
17
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