V53C16258SH 查看數據表（PDF） - Mosel Vitelic, Corp

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V53C16258SH

HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM SELF REFRESH

Mosel Vitelic, Corp 

MOSEL VITELIC

The Self Refresh mode is terminated by returning

the RAS clock to a high level for a specified (tRPS)

minimum time. After termination of the Self Refresh

cycle normal accesses to the device may be initiat-

ed immediately, providing that subsequent refresh

cycles utilize the CAS before RAS (CBR) mode of

operation.

Data Output Operation

The V53C16258SH Input/Output is controlled by

OE, CAS, WE and RAS. A RAS low transition

enables the transfer of data to and from the selected

row address in the Memory Array. A RAS high

transition disables data transfer and latches the

output data if the output is enabled. After a memory

cycle is initiated with a RAS low transition, a CAS

low transition or CAS low level enables the internal

I/O path. A CAS high transition or a CAS high level

disables the I/O path and the output driver if it is

enabled. A CAS low transition while RAS is high has

no effect on the I/O data path or on the output

drivers. The output drivers, when otherwise

enabled, can be disabled by holding OE high. The

OE signal has no effect on any data stored in the

output latches. A WE low level can also disable the

output drivers when CAS is low. During a Write

cycle, if WE goes low at a time in relationship to

CAS that would normally cause the outputs to be

active, it is necessary to use OE to disable the

output drivers prior to the WE low transition to allow

Data In Setup Time (tDS) to be satisfied.

V53C16258SH

Power-On

After application of the VCC supply, an initial

pause of 200 ms is required followed by a minimum

of 8 initialization cycles (any combination of cycles

containing a RAS clock). Eight initialization cycles

are required after extended periods of bias without

clocks (greater than the Refresh Interval).

During Power-On, the VCC current requirement of

the V53C16258SH is dependent on the input levels

of RAS and CAS. If RAS is low during Power-On,

the device will go into an active cycle and ICC will

exhibit current transients. It is recommended that

RAS and CAS track with VCC or be held at a valid

VIH during Power-On to avoid current surges.

Table 1. V53C16258SH Data Output

Operation for Various Cycle Types

Cycle Type

I/O State

Read Cycles

Data from Addressed

Memory Cell

CAS-Controlled Write

Cycle (Early Write)

High-Z

WE-Controlled Write

Cycle (Late Write)

OE Controlled. High

OE = High-Z I/Os

Read-Modify-Write

Cycles

Data from Addressed

Memory Cell

EDO Read Cycle

Data from Addressed

Memory Cell

EDO Write Cycle

(Early Write)

High-Z

EDO Read-Modify-

Write Cycle

Data from Addressed

Memory Cell

RAS-only Refresh

High-Z

CAS-before-RAS

Refresh Cycle

Data remains as in

previous cycle

CAS-only Cycles

High-Z

V53C16258SH Rev 0.2 Aug. 1998

17

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