V53C318165A-70K 查看數據表（PDF） - Mosel Vitelic, Corp

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V53C318165A-70K

3.3 VOLT 1M X 16 EDO PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic, Corp 

MOSEL VITELIC

Extended Data Output Page Mode

EDO Page operation permits all 1024 columns

within a selected row of the device to be randomly

accessed at a high data rate. Maintaining RAS low

while performing successive CAS cycles retains the

row address internally and eliminates the need to

reapply it for each cycle. The column address buffer

acts as a transparent or flow-through latch while

CAS is high. Thus, access begins from the occur-

rence of a valid column address rather than from the

falling edge of CAS, eliminating tASC and tT from the

critical timing path. CAS latches the address into the

column address buffer. During EDO operation,

Read, Write, Read-Modify-Write or Read-Write-

Read cycles are possible at random addresses

within a row. Following the initial entry cycle into

EDO Mode, access is tCAA or tCAP controlled. If the

column address is valid prior to the rising edge of

CAS, the access time is referenced to the CAS ris-

ing edge and is specified by tCAP. If the column ad-

dress is valid after the rising CAS edge, access is

timed from the occurrence of a valid address and is

specified by tCAA. In both cases, the falling edge of

CAS latches the address and enables the output.

EDO provides a sustained data rate of 50 MHz for

applications that require high bandwidth such as

bit-mapped graphics or high-speed signal process-

ing. The following equation can be used to calculate

the maximum data rate:

Data Rate = -t-R----C-----+-----11---00----22---43-----×-----t--P---C--

Self Refresh

Self Refresh mode provides internal refresh con-

trol signals to the DRAM during extended periods of

inactivity. Device operation in this mode provides

additional power savings and design ease by elimi-

nation of external refresh control signals. Self Re-

fresh mode is initialed with a CAS before RAS

(CBR) Refresh cycle, holding both RAS low (tRASS)

and CAS low (tCHD) for a specified period. Both of

these parameters are specified with minimum val-

ues to guarantee entry into Self Refresh operation.

Once the device has been placed in to Self Refresh

mode the CAS clock is no longer required to main-

tain Self Refresh operation.

V53C318165A

The Self Refresh mode is terminated by returning

the RAS clock to a high level for a specified (tRPS)

minimum time. After termination of the Self Refresh

cycle normal accesses to the device may be initiat-

ed immediately, poviding that subsequest refresh

cycles utilize the CAS before RAS (CBR) mode of

operation.

Data Output Operation

The V53C318165A Input/Output is controlled by

OE, CAS, WE and RAS. A RAS low transition en-

ables the transfer of data to and from the selected

row address in the Memory Array. A RAS high tran-

sition disables data transfer and latches the output

data if the output is enabled. After a memory cycle

is initiated with a RAS low transition, a CAS low

transition or CAS low level enables the internal I/O

path. A CAS high transition or a CAS high level dis-

ables the I/O path and the output driver if it is en-

abled. A CAS low transition while RAS is high has

no effect on the I/O data path or on the output driv-

ers. The output drivers, when otherwise enabled,

can be disabled by holding OE high. The OE signal

has no effect on any data stored in the output latch-

es. A WE low level can also disable the output driv-

ers when CAS is low. During a Write cycle, if WE

goes low at a time in relationship to CAS that would

normally cause the outputs to be active, it is neces-

sary to use OE to disable the output drivers prior to

the WE low transition to allow Data In Setup Time

(tDS) to be satisfied.

Power-On

After application of the VCC supply, an initial

pause of 200 µs is required followed by a minimum

of 8 initialization cycles (any combination of cycles

containing a RAS clock). Eight initialization cycles

are required after extended periods of bias without

clocks (greater than the Refresh Interval).

During Power-On, the VCC current requirement of

the V53C318165A is dependent on the input levels

of RAS and CAS. If RAS is low during Power-On,

the device will go into an active cycle and ICC will ex-

hibit current transients. It is recommended that RAS

and CAS track with VCC or be held at a valid VIH dur-

ing Power-On to avoid current surges.

V53C318165A Rev. 1.0 January 1998

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