V53C318165A-50T 查看數據表（PDF） - Mosel Vitelic, Corp
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V53C318165A-50T Datasheet PDF : 18 Pages
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MOSEL VITELIC
V53C318165A
Notes:
1. All voltage are referenced to VSS.
2. ICC1, ICC3, ICC4, and ICC7 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during an
EDO cycle (tHPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also mea-
sured between VIH and VIL.
7. Measured with a load equivalent to 2 TTL gates and 50 pF (VOL = 0.8V and VOH = 2.0V).
8. tOFF (max.) and tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not ref-
erenced to output voltage levels.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
11. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-
circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.), and
tCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
12. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only: if tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
13. Operation within the tRAD (max) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only: if tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
14. AC measurements assume tT = 2 ns.
15. Either tDZC or tDEO must be satisfied.
16. Either tCDD or tODD must be satisfied.
17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-
ation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR – Distributed/Burst; or CBR – Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
18. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
V53C318165A Rev. 1.0 January 1998
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