V54C316162V-6 查看數據表（PDF） - Mosel Vitelic, Corp
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V54C316162V-6
200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
Mosel Vitelic, Corp
V54C316162V-6 Datasheet PDF : 21 Pages
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MOSEL VITELIC
V54C316162V
AC Characteristics (1,2,3)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5
-55
-6
-7
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock and Clock Enable
1 tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5
–
5.5
–
6
–
7
–
ns
10
–
10
–
10
–
10
–
ns
2 tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
200
–
183
–
166
–
143 MHz
–
100
–
100
–
100
–
100 MHz
3 tAC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
5
–
5.3
–
5.5
–
5.5
ns
2
–
7
–
7
–
7
–
7
ns
3
4 tCH
Clock High Pulse Width
5 tCL
Clock Low Pulse Width
6 tT
Transition time
Setup and Hold Times
2.5
–
2.5
–
2.5
–
2.5
–
ns
2.5
–
2.5
–
2.5
–
2.5
–
ns
1
10
1
10
1
10
1
10
ns
7 tCMDS Command Setup Time
8 tAS
Address Setup Time
9 tDS
Data In Setup Time
10 tCKS
CKE Setup Time
11 tCMDH Command Hold Time
12 tAH
Address Hold Time
13 tDH
Data In Hold Time
14 tCKH
CKE Hold Time
Common Parameters
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
15 tRCD
Row to Column Delay Time
15
–
16.5
–
18
–
18
–
ns
5
16 tRAS
Row Active Time
40 100K 45 100K 48 100K 48 100K
ns
5
17 tRC
Row Cycle Time
60
–
63
–
66
–
70
–
ns
5
18 tRP
Row Precharge Time
15
–
17
–
18
–
21
–
ns
5
19 tRRD
Activate(a) to Activate(b) Com-
10
–
11
–
12
–
14
–
ns
5
mand
period
20 tCCD
CAS(a) to CAS(b) Command pe- 1
–
1
–
1
–
1
–
CLK
riod
21 tRCS
Mode Register Set-up time
10
–
11
–
12
–
14
–
ns
22 tSB
Power Down Mode Entry Time
0
5
0
5.5
0
6
0
7
ns
Refresh Cycle
23 tREF
Refresh Period (4096 cycles)
–
64
–
64
–
64
–
64
ms
V54C316162V Rev.2.9 September 2001
10
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