V54C316162 查看數據表（PDF） - Mosel Vitelic, Corp

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V54C316162

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Full Page Burst Write Operation

8.2 Termination of a Full Page Burst Write Operation

V54C316162V

V54C316162V Rev.2.9 September 2001

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